The invention relates to a method for fabricating an active transistor region in a bipolar technology on a substrate, and to an active transistor region which is fabricated by this method.
Integrated circuits having transistors with a high cut-off frequency are required for typical radiofrequency applications, such as wireless communications technology. The fabrication of integrated bipolar transistors with a high cut-off frequency of about fcut-off=50 GHz is technically complex. Integrated transistors, which are fabricated using bipolar technology, usually have a buried collector, which is fabricated by a process sequence, which first implants a dopant with low energy in a semiconductor substrate surface. A monocrystalline silicon layer having a specific thickness is subsequently deposited epitaxially, thereby producing a buried doping region. Afterward, further or additional steps are carried out for completing the transistors, such as, for instance, the application of additional layers for fabricating a base region and an emitter region.
DE 196 11 692 A1 describes a corresponding process for fabricating bipolar transistors in a CMOS-compatible silicon-germanium technology with the transistors having a dielectric strength of about VCEO=4 V. The transistors described in DE 196 11 692 can be used for applications up to a frequency of about 25 GHz.
The dielectric strength of the described transistors and the switching speed are essentially determined by the thickness of the epitaxial layer, which has a value of 0.8 xcexcm in the case of transistors in accordance with DE 196 11 692 A1. If the thickness of the epitaxial layer were increased, it would be possible to fabricate transistors with increased dielectric strength. This is not practicable, however, since the cut-off frequency of the transistor would be reduced by an increased thickness of the epitaxial layer.
It is an object of the present invention to further develop the above-described known fabrication method in such a way that it is possible to fabricate simultaneously transistors with a high dielectric strength and transistors with an increased cut-off frequency compared with the known method.
This object is achieved according to the invention by a method comprising the steps of providing a substrate, producing a buried doping region in the substrate, producing an epitaxial layer, which is doped more lightly than the buried doping region on the substrate, producing a retrograde doping profile in the epitaxial layer by either a single-stage or multi-stage high-energy implantation of suitable dopants so that the highly doped region of the buried doping region is enlarged in the direction of the substrate surface, and carrying out additional known method steps for completing the active transistor region.
The method according to the invention is particularly flexible since different types of semiconductor components can be fabricated in parallel on the same substrate. In the sense of the invention, the term xe2x80x9cdifferent typesxe2x80x9d means that it is possible to fabricate transistors which are optimized either with regard to the dielectric or voltage strength or with regard to the radiofrequency or high-frequency properties.
It is advantageous, moreover, that the process is not made unnecessarily complicated by the process steps that are additionally required according to the invention.
It is likewise advantageous that the process is fully CMOS-compatible but also BiCMOS-compatible.
According to the invention, a single-stage or multi-stage high-energy implantation is carried out which enables a retrograde doping profile to be fabricated in the epitaxial layer in a region of the substrate. The high-energy implantation is preferably effected in two stages. Preferably, the region of the retrograde doping directly adjoins the highly doped region of the buried doping region so that the size of the highly doped doping region is enlarged. The consequence of this is that it is possible to locally produce a transistor comparable to a transistor which is fabricated by means of a process in which the epitaxial layer has been fabricated comparatively thinner.
After the high-energy implantation, the method according to the invention is continued in a manner known per se for completing the desired transistors. If the intention is to fabricate an npn transistor in the relevant substrate region, then there follow process steps for fabricating a base zone and an emitter zone. On the other hand, if the intention is to fabricate a pnp transistor, there follow, in a manner known per se, modified steps for producing a complementary transistor. Reference is made to DE 196 11 692 A1 for example.
In a preferred embodiment, an oxide layer, for example a TEOS (tetraethylorthosilicate)layer having a thickness of preferably less than 400 nm, and preferably having a thickness in the range from 20 to 200 nm, is produced above the epitaxial layer. The application of the TEOS layer is generally followed by a densification of the TEOS layer by a thermal treatment. This layer is preferably fabricated before the high-energy doping. This is advantageous since the oxide layer acts as a screen oxide with regard to the implanted dopants.
In one development of the method, a p-doped polysilicon layer, for example, is produced before the high-energy doping above the oxide layer. This is followed by an etching step for producing an opening in the polysilicon layer above the active transistor region. The etching stops on the oxide layer lying below the polysilicon layer. Preferably, an arrangement for laterally limiting the propagation of the implanted dopants is produced, and, for example, a photoresist mask is provided above the p-type polysilicon layer. The opening in the laterally limiting arrangement is preferably chosen to be larger than the etched-in opening in the p-type polysilicon layer.
The invention also relates to a method for fabricating an arrangement which is integrated on a substrate and comprises transistors of a first type with a high breakdown voltage and transistors of a second type with a high cut-off frequency by using the method to fabricate the transistors of the second type in contrast to the transistors of the first type.
According to the invention, the method according to the invention is carried out in the region of the transistor of the second type. No high-energy implantation for enlarging the buried collector region is carried out in the region of the transistor of the first type. In this way, a comparatively thick epitaxial layer can be applied during the process on the entire substrate, resulting in a high dielectric strength in the case of the transistors of the first type.
The transistor regions thus essentially differ by the fact that in the region between the buried doping region and the base region different doping profiles are produced, or in the specific case a retrograde doping profile in the second type and no doping profile in the first type.
A doping profile according to the invention is to be understood as the profile of the doping concentration in the direction perpendicular to the main surface of the substrate through the active region of the transistor.
In the substrate region of the transistor of the first type, a planar doping profile is preferably produced by in-situ doping during the fabrication of the epitaxial layer. Preferably, a dopant is produced by means of beam implantation during the growth process. Preferably, the transistor of the first type has, in the region of the epitaxial layer, an essentially xe2x80x9cplanarxe2x80x9d doping profile in which the concentration of the dopant/dopants is essentially constant and lower than the dopant concentration in the highly doped region.
The method according to the invention can be used to fabricate an active transistor region in a semiconductor structure fabricated in bipolar technology and having a substrate, a buried doping region and an epitaxial layer, which is doped more lightly than the buried doping region, and a retrograde doping region with a doping concentration which rises from the surface of the substrate in the direction of the buried doping region is present in the epitaxial layer. Therefore, the present invention also relates to an active transistor region.
The thickness of the epitaxial layer is preferably at least 300 nm, and particularly at 500 nm.
According to the invention, it is possible to fabricate transistor regions for pnp transistors and npn transistors. If a pnp transistor region is fabricated, it is preferred to provide the region of the retrograde doping with an n-type doping using phosphorus, for example, as the dopant. In a region with a transistor region for an npn transistor, the region of the retrograde doping is preferably p-doped.
The transistor which can be fabricated according to the invention preferably has a silicon-germanium base. Such a base can be fabricated by means of the method of the selective epitaxial growth of a silicon-germanium layer.
Transistors which are optimized with regard to the radiofrequency properties and have a cut-off frequency fcut-off in the range from 70 to 100 GHz can be fabricated according to the invention. The dielectric strength UCEO of the transistor which is optimized with regard to the radiofrequency properties is preferably at least 2 V. The dielectric strength of the transistor which is optimized with regard to the breakdown voltage has UCEO preferably in the range of 3 to 7 V, in particular in the range of 5 to 6 V.